Recent trends in electronics have been towards miniaturization, reduced weight, and multifunctionality. In order to satisfy these pressing demands, multi chip packaging technology has been developed. The technology incorporates a plurality of IC chips of the same type or different type in a single package. The multi chip packaging technology is advantageous in terms of size, weight and mounting density as compared to the case where only one IC chip is mounted in the single package so that a plurality of packages is required for mounting the plurality of IC chips. In the conventional multi chip packaging technology, two IC chips of same type or different type are attached to the board in turn, and IC chips and the board are electrically connected using a wire-bonding method. The conventional multi chip packaging technology will be described below with reference to FIGS. 1 to 3.
FIG. 1 is a plan view of a package before encapsulation in accordance with one example of a conventional multi chip package; FIG. 2 is a cross sectional view taken along line 2—2 of FIG. 1; FIG. 3 is a cross sectional view taken along line 3—3 of FIG. 1.
As shown in FIGS. 1 through 3, the conventional multi chip package 110 includes a first IC chip 111 having chip pads 112 along two edges of the chip and a second IC chip 113 having a row of chip pads 114 along the center of the chip. The first chip 111 is attached to the board 121 with an adhesive 151 and the second chip 113 is attached to the first chip 111 with an adhesive 153. The active surfaces of chips 111 and 113, on which the integrated circuits are formed, face the same direction. The first chip 111 and second chip 113 are electrically connected to the board 121 by wire-bonding chip pads 112 and 114 to the corresponding board pads 123 using bonding wires 141 and 143. Since the chip pads 114 of the second chip 113 are far from the board pads 123, the bonding wires 143 of the second chip 113 have long loops. As a result, problems such as cutting, sagging, and short-circuit of the bonding wires 143 are prevalent.
As an alternative method for solving the above problems, pad redistribution methods or the use of special bonding wires has been proposed. With the pad redistribution method, the chip pads of the second chip 113 are moved from the center to the edge of the chip. However, because this method requires many additional processes to form several more layers on the chip, the processing cost and time increase. Furthermore, the density of devices on the chip decreases because the pad redistribution method requires separate processes based on the IC chip and wafer sizes. For example, in the case where special gold (Au) bonding wires coated with a polymer material is used, the cost of the bonding wires is much more expensive and the manufacturing cost of the package is greatly increased.
As another alternative, a method used in ceramic packaging can be adopted. That is, a separate IC chip or jumper chip is attached to the board around the second chip. More specifically, by wire bonding the second chip to the jumper chip and then wire bonding the jumper chip to the board, the bonding wires of the second chip no longer have long fragile loops. However, because the number of jumper chips required is equal to the number of bonding wires, there are many drawbacks in terms of size, weight and manufacturing cost.